1. Field of the Invention
The present invention generally relates to a high-speed BiCMOS double sampling track-and-hold amplifier circuit; in particular, the present invention relates to a double sampling track-and-hold amplifier circuit combining the advantages of high transduction and double sampling offered by BiCMOS. The present invention uses the approach of double sampling to reduce complexities in designing the sampling circuit and the output buffer within the BiCMOS track-and-hold amplifier circuit thereby increasing the effective sampling rate to two times.
2. Description of Related Art
At present, the development of portable electronic products keeps devoting efforts in fulfilling goals of multiple functions, low power consumption, reduced costs and miniaturization in size, thus leading to the emergence of single-chip system concept, and relevant technologies now become considerably mature as well. In most of current single-chip systems the analog-to-digital converter is an indispensible component, and the analog-to-digital converter architecture may vary with regards to different applications and purposes.
In an analog-to-digital converter, the most critical unit should be the track-and-hold amplifier (THA) circuit. A well-designed track-and-hold amplifier circuit can not only elevate dynamic performance of the analog-to-digital converter, but extensively compress undesirable influences caused by clock skew and clock jitter problems of clock signals on the analog-to-digital converter.
Common track-and-hold amplifier circuits can be largely classified into of closed-circuit type and open-circuit type. Herein, the advantage of the closed-circuit architecture lies in high resolution, but it is inoperable under high frequency state. Consequently, the key consideration in applications of closed-circuit track-and-hold amplifier circuit is about the issue of circuit stability. But the solution to such an issue may also adversely complicate the design of high-speed track-and-hold amplifier circuit, accordingly consuming more power.
As a result, in high-speed domains, it is common to adopt the open-circuit type of architecture. In general, the open-circuit track-and-hold amplifier circuit architecture can be largely categorized as fully differential track-and-hold amplifier circuit and fully pseudo-differential track-and-hold amplifier circuit. It can be seen from FIG. 1 that the fully differential track-and-hold amplifier circuit 1 essentially comprises an input buffer 11 including two input ends and two output ends, two switches 12 and an output buffer 13 including two input ends and two output ends. On the other hand, the fully pseudo-differential track-and-hold amplifier circuit 2 as shown in FIG. 2 mainly comprises two input buffers 21 respectively including one input end and one output end, two switches 22 as well as two output buffers 23 respectively including one input end and one output end.
However, for actual applications, the track-and-hold amplifier circuit may not be so ideal. The output voltage of an ideal track-and-hold amplifier circuit should be maintained at a constant value, but in fact several non-ideal effects, such as hold mode feedthrough (HMF), pedestal error, droop error and the like, do exist, and all of which may cause the output of the track-and-hold amplifier circuit to fluctuate. In general, there are three major non-ideal effects existing in the track-and-hold amplifier circuit 3. The first one is pedestal error whose transduction pathway is shown in FIG. 3, and it can be been that such an error appears because, as the switch 31 performing connect and disconnect operations, the clock signal passes through the pathway of the stray capacitor 32 and couples to the sampling capacitor 33 used for signal storage. Hence, the amount of electric charge stored in the sampling capacitor 33 is affected, and the influence thereof on the output waveform is illustrated as reference number 37 in FIG. 3B.
The second non-ideal effect is droop error. From its transduction pathway shown in FIG. 3A, it can be seen that such an error occurs because, as the switch 31 performing the disconnect operation, the input impedance of the back-end buffer 34 is not an ideal infinity value but a finite input impedance. Therefore, a pathway of leakage current 35 may be formed at the input end of the back-end buffer 34 and such a leakage current 35 can result in gradual leakage of charge stored in the tracking capacitor 33, accordingly undesirable reduction of the voltage level. The influence of droop error on the output waveform is illustrated as reference number 38 in FIG. 3B.
Also, the third one is known as the hold mode feedthrough (HMF) effect. From its transduction pathway shown in FIG. 3A, it can be observed that such an error appears because, as the switch 31 performing the disconnect operation, the clock signal passes through the pathway of the stray capacitor 36 and couples to the sampling capacitor 33 used for signal storage, thus affecting the amount of charge stored in the sampling capacitor 33. The influence of hold mode feedthrough error on the output waveform is illustrated as reference number 39 in FIG. 3B. The reason that such an effect may occur is because a stray capacitor 36 exists between the input end and the output end of the component; hence, as the switch 31 disconnects, the input signal is not completely isolated, but rather couples to the output end of the switch 31 through the stray capacitor 36, further affecting the charge stored in the sampling capacitor 33 and accordingly resulting in distortion in THA output; therefore, the HMF issue is actually the most crucial factor that affects the resolution of THA.
In addition, currently the hold circuits concerning double sampling all apply CMOS processes, but one significant drawback caused by such CMOS processes is inoperability under high-speed state, and the amplitude of input/output signal is thus adversely restricted. As such, in order to successfully apply the hold circuit featuring double sampling under high-speed state, it is possible to use the double sampling method to reduce the complexities in designing the sampling circuit and the output buffer inside the high-speed track-and-hold amplifier circuit thereby increasing the effective sampling rate to two times; meanwhile, it is possible as well to adopt the linearization technology to enhance the linearity of the input buffer such that the dynamic response of the integral BiCMOS track-and-hold amplifier circuit can be improved. In this way an optimal solution can be achieved.